TS na load na sya sa preloader kaso loop lang sya preloader_b dahil sa cert vfy fail.
Ito po UART log ko
Pll init start...
Pll init Done!!
mtcmos Start..
efuse of id : hsmtop is 1
mtcmos Done!
PLL Preloader mode
PLL Preloader mode ret 0
#T#PLL=2
bandgap filter: 0x1000C010 = 0x100F00
pcie 0x112800c0 = 0xFC1
#T#GPIO=0
[DDR Reserve] DRM_DEBUG_CTL (0x1000d030): 0x83F1
[DDR Reserve] WDT_DEBUG_CTL_2(0x10007048): 0x1FFFF
[DDR Reserve] WDT_DEBUG_CTL_3(0x100070A8): 0x218000
[DDR Reserve] MTK_DRM_DEBUG_0_REG(0x1000D500): 0xC
[DDR Reserve] DRAMC_AO_CHA + 0xD00(0x10230D00): 0x0
[DDR Reserve] DDRPHY_AO_CHA + 0x1520(0x10239520): 0x0
[DDR Reserve] DRAMC_NAO_CHA + 0x80(0x10234080): 0x40060386
[DDR Reserve] DRAMC_NAO_CHA + 0x84(0x10234084): 0x10000000
[DDR Reserve] DRAMC_NAO_CHA + 0x88(0x10234088): 0x0
[DDR Reserve] DRAMC_AO_CHB + 0xD00(0x10240D00): 0x0
[DDR Reserve] DDRPHY_AO_CHB + 0x1520(0x10249520): 0x0
[DDR Reserve] DRAMC_NAO_CHB + 0x80(0x10244080): 0x40060386
[DDR Reserve] DRAMC_NAO_CHB + 0x84(0x10244084): 0x10000000
[DDR Reserve] DRAMC_NAO_CHB + 0x88(0x10244088): 0x0
[RGU] rst from: pl
[RGU] MODE: 0x35
[RGU] STA: 0x40000000
[RGU] LENGTH: 0xFFE0
[RGU] INTERVAL: 0xFFF
[RGU] SWSYSRST: 0x0
[RGU] LATCH_CTL: 0x21E71
[RGU] NONRST_REG: 0x0
[RGU] NONRST_REG2: 0x24002000
[RGU] DEBUG_CTL: 0x0
[RGU] DEBUG_1_REG: 0x40000000
[RGU] parse g_rgu_status: 2 (0x2)
[RGU] Set NONRST_REG to 0x40000000
[RGU] mtk_wdt_mode_config mode value=30, tmp:22000030
[DOE_ENV]get_env apwdt_en
[RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDE G_EN2(800067D2)
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x0
[RGU] rgu_update_reg: 0, bits: 0x300, addr: 0x100070A0, val: 0x0
[RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL(0x0)
[RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL2(0x0)
[RGU] mtk_wdt_pre_init: MTK_WDT_LATCH_CTL(0x21E71)
[DOE_ENV]get_env apwdt_en
[DOE_ENV]get_env apwdt_en
[DOE_ENV]get_env apwdt_en
[RGU] mtk_wdt_pre_init: MTK_WDT_REQ_MODE(1F0073), MTK_WDT_REQ_IRQ_EN(1B0070)
#T#WDT_PRE=21
RAM_CONSOLE_PL using SRAM
RAM_CONSOLE_PL start: 0x11D000, size: 0x800, sig: 0x43474244
RAM_CONSOLE_PL preloader last status: 0x0 0x0 0x0
RAM_CONSOLE_PL wdt status (0x2)=0x2
#T#Ram console=2
[PMIF] PLL_ULPOSC1_CON0/1/2 0x38A954 0x52E000 0x400000
[PMIF] ULPOSC1 K done: 261M
[pmifclkmgr_set_spmi_m_clk] done
[pmifclkmgr_set_spmi_p_clk] done
#T#PMIFCLKMGR=2
[SPMI] spmi_read_check done, slvid:4
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
record read addr=0xA0F, data=0x20, cmd=6
record write addr=0xA0F, data=0x20, cmd=3
record read addr=0xA2B, data=0x0, cmd=6
record write addr=0xA2B, data=0x29, cmd=3
record read addr=0xA2C, data=0x0, cmd=6
record write addr=0xA2C, data=0x47, cmd=3
record read addr=0xA0F, data=0x20, cmd=6
record write addr=0xA0F, data=0x20, cmd=3
record read addr=0xA0F, data=0x20, cmd=6
record write addr=0xA0F, data=0x20, cmd=3
record read addr=0xA2B, data=0x29, cmd=6
record write addr=0xA2B, data=0x0, cmd=3
record read addr=0xA2C, data=0x47, cmd=6
record write addr=0xA2C, data=0x0, cmd=3
record read addr=0x18, data=0x6, cmd=6
record write addr=0x42C, data=0x80, cmd=3(the last)
[SPMI] spmi_read_check done, slvid:4
[SPMI] rcs_en dly:0, pol:1, sampl:0x1
[SPMI] spmi_read_check done, slvid:5
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
[SPMI] spmi_read_check done, slvid:5
[SPMI] rcs_en dly:0, pol:1, sampl:0x1
#T#SPMI=11
[SPMI] spmi_read_check done, slvid:4
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
#T#SPMI_P=1
#T#I2C=0
DATE_CODE_YY:0, DATE_CODE_WW:0
[SegCode] Segment Code:0x2, PROJECT_CODE:0x0, FAB_CODE:0x0, RW_STA:0x992, CTL:0x 0, DCM:0x7
#T#DEVINFO=2
[PMIC]Preloader Start
[PMIC] CHIP Code = 0x3030
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x13C]=0x48
[PMIC]PONSTS[0xC]=0x24
[PMIC]POFFSTS[0xE]=0x400
[PMIC]TOPSTS[0x18]=0x6
[pmic_check_rst] AP Watchdog
[PMIC]just_rst = 0
[PMIC]RG_RSV_SWREG[0xA0D]=0x0
[pwrkey_dbg_status] powerkey:0 count=0(ms) g_pwrkey_release=0
[pmic_wdt_set] TOP_RST_MISC1=0x25
register vmd12 OK
register vrfdig OK
register vcore OK
register vmd11 OK
register vsram_md OK
register vsram_core OK
register vsram_proc OK
register vsram_rfdig OK
register vio18_2 OK
register vmdd2_no_used OK
register vefuse OK
register vio18_1 OK
register vmddr OK
register vmddq OK
[MT6315]S5 RG_SLV_ID[0x136]=0xB5
[MT6315]S5 TOP_RST_STATUS[0x129]=0x3
[MT6315]S5 POFFSTS[0xC]=0x0
[MT6315]S5 RGS_POFFSTS[0xA0F]=0x0
[MT6315]S5 PG_SDN_STS0[0xF]=0xF
[MT6315]S5 OC_SDN_STS0[0x10]=0x0
[MT6315]S5 BUCK_OC_SDN_STS[0x1416]=0x0
[MT6315]S5 BUCK_OC_SDN_EN[0x1451]=0x1F
[MT6315]S5 TOP_RST_MISC[0x126]=0x4
register vproc OK
[MT6315]latch vproc 750000 uV(0x44)
register vmdd2 OK
[MT6315]latch vmdd2 1125000 uV(0xEE)
[MT6315]S5 set TOP_RST_MISC=0x3
0xFFFF:0xFFFF:0xFFFF:0xFFFF:0x4694:0xA83B:0xFB89:0x1EF6
S5)
[MT6315]mt6315_spmi_probe done
[PMIC]Init done
[pmic_enable_smart_reset] smart_en:0, smart_sdn_en:0
#T#PMIC=19
vproc/vsram run as hw default
[RGU] mtk_wdt_mode_config mode value=30, tmp:22000030
[RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D
[RGU] g_rgu_status: 2 (0x2)
[DOE_ENV]get_env apwdt_en
[RGU] bypass pwrkey: set
#T#WDT_INIT=3
RAM_CONSOLE_PL wdt status (0x2)=0x2
#T#Ram console=0
[SD0] Host controller intialization start
MSDC0 HCLK_MUX[0x1000_0020][17:16] = 1, pdn = 0, CLK_MUX[0x1000_0020][26:24] = 1 , pdn = 0, CLK_CG[0x1000_1094] bit2 = 0, bit6 = 0
MSDC0 MODE5[10005350] = 0x11111000 should: 0x11111???
MSDC0 MODE6[10005360] = 0x01111111 should: 0x?1111111
MSDC0 IES [11E00030] = 0x001FFFFF should: 0x????1FFE
MSDC0 SMT [11E000D0] = 0x000FFFFF should: 0x?????FFF
MSDC0 TDSEL0_0[11E000F0] = 0x00000000,[11E00100] = 0x00000000 should: 0x000000 00MSDC0, should: 0x????0000
MSDC0 RDSEL0[11E00090] = 0x00000000, [11E000A0] = 0x00000000, [11E000B0] = 0x000 00000 should: 0x00000000 ,should: 0x00000000 ,should: 0x??????00
MSDC0 DRV0 [11E00000] = 0x09249249, [11E00010] = 0x00249249 should: 0x?92492 49, should: 0x???????9
PUPD/R1/R0: dat/cmd:0/0/1, clk/dst: 1/1/0
MSDC0 PUPD0 [11E00050] = 0x0003F401 should: 0x?????401
MSDC0 R0 [11E00070] = 0x0003EBFE should: 0x?????BFE
MSDC0 R1 [11E00080] = 0x00001401 should: 0x?????401
[SD0] SET_CLK(260kHz): SCLK(260kHz) MODE(0) DDR(0) DIV(400) DS(0) RS(0)
[SD0] Host controller intialization done
[mmc_init]: msdc0 start mmc_init_card()
[mmc_init_card]: start
[SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB
[SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024
[SD0] Switch to High-Speed mode!
[SD0] Switch to SDR buswidth
[SD0] SET_CLK(260kHz): SCLK(260kHz) MODE(0) DDR(0) DIV(400) DS(0) RS(0)
[SD0] Size: 29820 MB, Max.Speed: 52000 kHz, blklen(512), nblks(61071360)
[SD0] Initialized, eMMC45
[SD0] SET_CLK(52000kHz): SCLK(52000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0)
[mmc_init_card]: finish successfully
#T#Boot dev init=168
[PLFM] Init Boot Device: OK(0)
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB
[SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024
[AB] Current boot: Preloader_a
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[QL_AB] metadata.slots[0].priority:15,metadata.slots[1].priority:0.
[AB] ab_suffix: _a, ab_retry: 0, ab_boot_success: 1
[ROM_INFO] 'v131074'
[LIB] Loading SEC config
[LIB] Name =
[LIB] Config = 0x22, 0x11
0x31,0x41,0x35,0x32
GCPU Enhance,PL_V1.4
[SEC] reading seccfg
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
[LIB] seclib_img_auth_load_sig [LIB] CFG read size '0x2000' '0x3C'
[LIB] SEC CFG doesn't exist
[SEC] init fail '0x103000'
#T#Sec lib init=30
[SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB
[SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024
boot_part: 1
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
part name=loader_ext_a
[SEC_POLICY] reached the end, use default policy
[SEC_POLICY] sboot_state = 0x1
[SEC_POLICY] lock_state(default) = 0x4
img_auth_required=1
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
sbc_en = 0
[SBC] cert verify, part = loader_ext_a, img = loader_ext_dram...fail, ret = 0x10 1017
cert vfy fail
<ASSERT> /101g/mtk/package/boot/preloader/platform/mt6890/src/core/main.c:line 1 047 0
PL fatal error...
PL delay for Long Press Reboot
[PLFM] emergency download mode(timeout: 5s).
[RGU] mtk_arch_reset at pre-loader!
[RGU] mtk_wdt_reset WDT MODE=35
Ito po UART log ko
Pll init start...
Pll init Done!!
mtcmos Start..
efuse of id : hsmtop is 1
mtcmos Done!
PLL Preloader mode
PLL Preloader mode ret 0
#T#PLL=2
bandgap filter: 0x1000C010 = 0x100F00
pcie 0x112800c0 = 0xFC1
#T#GPIO=0
[DDR Reserve] DRM_DEBUG_CTL (0x1000d030): 0x83F1
[DDR Reserve] WDT_DEBUG_CTL_2(0x10007048): 0x1FFFF
[DDR Reserve] WDT_DEBUG_CTL_3(0x100070A8): 0x218000
[DDR Reserve] MTK_DRM_DEBUG_0_REG(0x1000D500): 0xC
[DDR Reserve] DRAMC_AO_CHA + 0xD00(0x10230D00): 0x0
[DDR Reserve] DDRPHY_AO_CHA + 0x1520(0x10239520): 0x0
[DDR Reserve] DRAMC_NAO_CHA + 0x80(0x10234080): 0x40060386
[DDR Reserve] DRAMC_NAO_CHA + 0x84(0x10234084): 0x10000000
[DDR Reserve] DRAMC_NAO_CHA + 0x88(0x10234088): 0x0
[DDR Reserve] DRAMC_AO_CHB + 0xD00(0x10240D00): 0x0
[DDR Reserve] DDRPHY_AO_CHB + 0x1520(0x10249520): 0x0
[DDR Reserve] DRAMC_NAO_CHB + 0x80(0x10244080): 0x40060386
[DDR Reserve] DRAMC_NAO_CHB + 0x84(0x10244084): 0x10000000
[DDR Reserve] DRAMC_NAO_CHB + 0x88(0x10244088): 0x0
[RGU] rst from: pl
[RGU] MODE: 0x35
[RGU] STA: 0x40000000
[RGU] LENGTH: 0xFFE0
[RGU] INTERVAL: 0xFFF
[RGU] SWSYSRST: 0x0
[RGU] LATCH_CTL: 0x21E71
[RGU] NONRST_REG: 0x0
[RGU] NONRST_REG2: 0x24002000
[RGU] DEBUG_CTL: 0x0
[RGU] DEBUG_1_REG: 0x40000000
[RGU] parse g_rgu_status: 2 (0x2)
[RGU] Set NONRST_REG to 0x40000000
[RGU] mtk_wdt_mode_config mode value=30, tmp:22000030
[DOE_ENV]get_env apwdt_en
[RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D
[RGU] mtk_wdt_reset_deglitch_enable: MTK_WDT_RSTDEG_EN1(8000A357), MTK_WDT_RSTDE G_EN2(800067D2)
[RGU] rgu_update_reg: 0, bits: 0xC000, addr: 0x10007040, val: 0x0
[RGU] rgu_update_reg: 0, bits: 0x300, addr: 0x100070A0, val: 0x0
[RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL(0x0)
[RGU] mtk_wdt_pre_init: MTK_WDT_DEBUG_CTL2(0x0)
[RGU] mtk_wdt_pre_init: MTK_WDT_LATCH_CTL(0x21E71)
[DOE_ENV]get_env apwdt_en
[DOE_ENV]get_env apwdt_en
[DOE_ENV]get_env apwdt_en
[RGU] mtk_wdt_pre_init: MTK_WDT_REQ_MODE(1F0073), MTK_WDT_REQ_IRQ_EN(1B0070)
#T#WDT_PRE=21
RAM_CONSOLE_PL using SRAM
RAM_CONSOLE_PL start: 0x11D000, size: 0x800, sig: 0x43474244
RAM_CONSOLE_PL preloader last status: 0x0 0x0 0x0
RAM_CONSOLE_PL wdt status (0x2)=0x2
#T#Ram console=2
[PMIF] PLL_ULPOSC1_CON0/1/2 0x38A954 0x52E000 0x400000
[PMIF] ULPOSC1 K done: 261M
[pmifclkmgr_set_spmi_m_clk] done
[pmifclkmgr_set_spmi_p_clk] done
#T#PMIFCLKMGR=2
[SPMI] spmi_read_check done, slvid:4
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
record read addr=0xA0F, data=0x20, cmd=6
record write addr=0xA0F, data=0x20, cmd=3
record read addr=0xA2B, data=0x0, cmd=6
record write addr=0xA2B, data=0x29, cmd=3
record read addr=0xA2C, data=0x0, cmd=6
record write addr=0xA2C, data=0x47, cmd=3
record read addr=0xA0F, data=0x20, cmd=6
record write addr=0xA0F, data=0x20, cmd=3
record read addr=0xA0F, data=0x20, cmd=6
record write addr=0xA0F, data=0x20, cmd=3
record read addr=0xA2B, data=0x29, cmd=6
record write addr=0xA2B, data=0x0, cmd=3
record read addr=0xA2C, data=0x47, cmd=6
record write addr=0xA2C, data=0x0, cmd=3
record read addr=0x18, data=0x6, cmd=6
record write addr=0x42C, data=0x80, cmd=3(the last)
[SPMI] spmi_read_check done, slvid:4
[SPMI] rcs_en dly:0, pol:1, sampl:0x1
[SPMI] spmi_read_check done, slvid:5
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
[SPMI] spmi_read_check done, slvid:5
[SPMI] rcs_en dly:0, pol:1, sampl:0x1
#T#SPMI=11
[SPMI] spmi_read_check done, slvid:4
[SPMI] non-rcs dly:0, pol:1, sampl:0x1
#T#SPMI_P=1
#T#I2C=0
DATE_CODE_YY:0, DATE_CODE_WW:0
[SegCode] Segment Code:0x2, PROJECT_CODE:0x0, FAB_CODE:0x0, RW_STA:0x992, CTL:0x 0, DCM:0x7
#T#DEVINFO=2
[PMIC]Preloader Start
[PMIC] CHIP Code = 0x3030
[PMIC]POWER_HOLD :0x1
[PMIC]TOP_RST_STATUS[0x13C]=0x48
[PMIC]PONSTS[0xC]=0x24
[PMIC]POFFSTS[0xE]=0x400
[PMIC]TOPSTS[0x18]=0x6
[pmic_check_rst] AP Watchdog
[PMIC]just_rst = 0
[PMIC]RG_RSV_SWREG[0xA0D]=0x0
[pwrkey_dbg_status] powerkey:0 count=0(ms) g_pwrkey_release=0
[pmic_wdt_set] TOP_RST_MISC1=0x25
register vmd12 OK
register vrfdig OK
register vcore OK
register vmd11 OK
register vsram_md OK
register vsram_core OK
register vsram_proc OK
register vsram_rfdig OK
register vio18_2 OK
register vmdd2_no_used OK
register vefuse OK
register vio18_1 OK
register vmddr OK
register vmddq OK
[MT6315]S5 RG_SLV_ID[0x136]=0xB5
[MT6315]S5 TOP_RST_STATUS[0x129]=0x3
[MT6315]S5 POFFSTS[0xC]=0x0
[MT6315]S5 RGS_POFFSTS[0xA0F]=0x0
[MT6315]S5 PG_SDN_STS0[0xF]=0xF
[MT6315]S5 OC_SDN_STS0[0x10]=0x0
[MT6315]S5 BUCK_OC_SDN_STS[0x1416]=0x0
[MT6315]S5 BUCK_OC_SDN_EN[0x1451]=0x1F
[MT6315]S5 TOP_RST_MISC[0x126]=0x4
register vproc OK
[MT6315]latch vproc 750000 uV(0x44)
register vmdd2 OK
[MT6315]latch vmdd2 1125000 uV(0xEE)
[MT6315]S5 set TOP_RST_MISC=0x3
0xFFFF:0xFFFF:0xFFFF:0xFFFF:0x4694:0xA83B:0xFB89:0x1EF6
S5)[MT6315]mt6315_spmi_probe done
[PMIC]Init done
[pmic_enable_smart_reset] smart_en:0, smart_sdn_en:0
#T#PMIC=19
vproc/vsram run as hw default
[RGU] mtk_wdt_mode_config mode value=30, tmp:22000030
[RGU] mtk_wdt_mode_config mode value=7D, tmp:2200007D
[RGU] g_rgu_status: 2 (0x2)
[DOE_ENV]get_env apwdt_en
[RGU] bypass pwrkey: set
#T#WDT_INIT=3
RAM_CONSOLE_PL wdt status (0x2)=0x2
#T#Ram console=0
[SD0] Host controller intialization start
MSDC0 HCLK_MUX[0x1000_0020][17:16] = 1, pdn = 0, CLK_MUX[0x1000_0020][26:24] = 1 , pdn = 0, CLK_CG[0x1000_1094] bit2 = 0, bit6 = 0
MSDC0 MODE5[10005350] = 0x11111000 should: 0x11111???
MSDC0 MODE6[10005360] = 0x01111111 should: 0x?1111111
MSDC0 IES [11E00030] = 0x001FFFFF should: 0x????1FFE
MSDC0 SMT [11E000D0] = 0x000FFFFF should: 0x?????FFF
MSDC0 TDSEL0_0[11E000F0] = 0x00000000,[11E00100] = 0x00000000 should: 0x000000 00MSDC0, should: 0x????0000
MSDC0 RDSEL0[11E00090] = 0x00000000, [11E000A0] = 0x00000000, [11E000B0] = 0x000 00000 should: 0x00000000 ,should: 0x00000000 ,should: 0x??????00
MSDC0 DRV0 [11E00000] = 0x09249249, [11E00010] = 0x00249249 should: 0x?92492 49, should: 0x???????9
PUPD/R1/R0: dat/cmd:0/0/1, clk/dst: 1/1/0
MSDC0 PUPD0 [11E00050] = 0x0003F401 should: 0x?????401
MSDC0 R0 [11E00070] = 0x0003EBFE should: 0x?????BFE
MSDC0 R1 [11E00080] = 0x00001401 should: 0x?????401
[SD0] SET_CLK(260kHz): SCLK(260kHz) MODE(0) DDR(0) DIV(400) DS(0) RS(0)
[SD0] Host controller intialization done
[mmc_init]: msdc0 start mmc_init_card()
[mmc_init_card]: start
[SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB
[SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024
[SD0] Switch to High-Speed mode!
[SD0] Switch to SDR buswidth
[SD0] SET_CLK(260kHz): SCLK(260kHz) MODE(0) DDR(0) DIV(400) DS(0) RS(0)
[SD0] Size: 29820 MB, Max.Speed: 52000 kHz, blklen(512), nblks(61071360)
[SD0] Initialized, eMMC45
[SD0] SET_CLK(52000kHz): SCLK(52000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0)
[mmc_init_card]: finish successfully
#T#Boot dev init=168
[PLFM] Init Boot Device: OK(0)
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB
[SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024
[AB] Current boot: Preloader_a
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[QL_AB] metadata.slots[0].priority:15,metadata.slots[1].priority:0.
[AB] ab_suffix: _a, ab_retry: 0, ab_boot_success: 1
[ROM_INFO] 'v131074'
[LIB] Loading SEC config
[LIB] Name =
[LIB] Config = 0x22, 0x11
0x31,0x41,0x35,0x32
GCPU Enhance,PL_V1.4
[SEC] reading seccfg
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
[LIB] seclib_img_auth_load_sig [LIB] CFG read size '0x2000' '0x3C'
[LIB] SEC CFG doesn't exist
[SEC] init fail '0x103000'
#T#Sec lib init=30
[SD0] EXT_CSD_ERASE_GRP_DEF is Off, wp_size = 8192KB
[SD0] csd.write_prot_grpsz = 15, csd.erase_sctsz = 1024
boot_part: 1
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
part name=loader_ext_a
[SEC_POLICY] reached the end, use default policy
[SEC_POLICY] sboot_state = 0x1
[SEC_POLICY] lock_state(default) = 0x4
img_auth_required=1
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
[GPT_PL]check header, err(signature 0x00000054594C5242!=0x5452415020494645)
[GPT_PL] get_gpt_header fail
sbc_en = 0
[SBC] cert verify, part = loader_ext_a, img = loader_ext_dram...fail, ret = 0x10 1017
cert vfy fail
<ASSERT> /101g/mtk/package/boot/preloader/platform/mt6890/src/core/main.c:line 1 047 0
PL fatal error...
PL delay for Long Press Reboot
[PLFM] emergency download mode(timeout: 5s).
[RGU] mtk_arch_reset at pre-loader!
[RGU] mtk_wdt_reset WDT MODE=35
